Every year, new microelectronic technologies are available, affording innovations and improvements to our daily life. All this is possible by virtue of circuits of ever higher performance and ever more complex functions. This increase in performance has been made possible through the miniaturization of elementary components, namely transistors. Current technologies make it possible to design microchips having transistors with atomic dimensions. As the size of the transistors is reduced towards some ten nanometers, the variation of the dopants in the region of the channel directly causes a variation of the threshold voltage VTH between two transistors assumed to be identical and adjacent on one and the same microchip. Novel structures of MOSFET transistors have recently been proposed so as to reduce the variability of the components below 22 nm, some according to FinFet technology which uses multi-gate non-planar transistors, and others according to FDSOI “Fully Depleted Silicon On Insulator” technology.
FDSOI (Fully Depleted Silicon on Insulator) technology is based on a thin (5 to 20 nm) layer of silicon on a thin (5 to 50 nm) buried oxide (Buried Oxide—BOx) layer. The transistors are constructed on the fine non-doped silicon layer (depleted of charge) which has several advantages with respect to the Bulk. As the channel is completely depleted, the random variation of the dopants which impinged on the Bulk CMOS is reduced, thereby improving the performance at lower VDD. FDSOI claims an improvement in the Consumption/Performance ratio of the order of 30 to 40% versus 20 nm Bulk CMOS.
However, the variability of the fabrication methods remains constraining for integrated circuits and it introduces mismatches of the transistors. Thus on one and the same microchip, transistors assumed to be identical will not have the same characteristics. This difference in characteristics may introduce malfunctions of the final circuit, which may then no longer satisfy, for certain applications, the specifications demanded.
In the specific case of analogue electronics, certain cells require the transistors to be identical, that is to say matched. Techniques for calibrating circuits have become necessary for a majority of applications.
However, the known approaches for the implementation of calibration lead to an increase in the surface area of the final circuit through extra electronics, therefore to an increase in consumption and to an increase in overall cost.
Hence a problem to be solved is that of proposing a calibration solution for circuits which does not increase the surface area of the circuit, and which exhibits an immunity to the variability of the methods.
FDSOI technology which does not need any doping to control the threshold voltage, and which moreover offers on the transistors a back gate, makes it possible to propose a calibration solution based on the control of the back gate of the transistors.
However, in the case of differential analogue circuits, such as current mirrors or differential pairs, it is important that the transistors have the same characteristics. Likewise, to produce oscillators, especially ring oscillators based on inverters, it is also important that the transistors (therefore the inverters) have the same characteristics so as to decrease the phenomenon of jitter. However, no known simple solution to this problem exists in FDSOI technology.
Therefore the need exists for a solution which alleviates the drawbacks of the known approaches. The present invention addresses this need. This invention applies to all digital circuits using complementary logic.